AI in Design Verification: What DVCon 2025–2026 Tells Us
DVCon has turned into the place where verification teams show what they actually built with AI, not what they hope to build. Between DVCon Europe in Munich last October and DVCon U.S. in Santa Clara this March, roughly two dozen papers and tutorials carried AI, LLM, or agent in the title, and NVIDIA's keynote and the headline panel were both about whether AI can end the verification bottleneck.
This post is a reading guide. I read the proceedings PDFs for the papers below and grouped them into five themes, each with a short take on what is genuinely new, what the numbers really say, and where I would be careful. Follow the title links for the papers themselves; they are free on the DVCon proceedings archive.
- 1. Debug and root cause
- 2. Regression and coverage closure
- 3. AI meets formal
- 4. Spec grounding and design understanding
- 5. Honest case studies, benchmarks, and cost
The one-paragraph version
Debug is where the strongest results are. The award-placed paper of the year is an LLM that explains formal counterexamples, and three separate Samsung teams reported log, waveform, and triage assistants with large claimed time savings. Regression management is the second cluster, and the interesting work there is architectural (tiers, gates, message brokers) rather than model-driven. Formal verification is the surprise growth area, because a model checker gives the LLM ground truth it cannot fake. And the field is maturing: this year's papers include cost accounting, open benchmarks, and case studies that report failures as readily as wins.
Debug and root cause: the clearest wins
Every team has the same overnight-regression morning: hundreds of failures, and the first hour of each one is spent collecting logs, configs, and history before any thinking starts. That collection step is exactly what LLMs and small embedding models are good at, which is why this theme has the most deployed-in-production stories.
ProblemAfter an overnight regression an engineer burns 30 to 60 minutes per failure just collecting logs, config files, spec data, and similar past cases before any real analysis begins.
ApproachA LangGraph pipeline of five agents (Error Analyzer, Data Collector, Decision Maker, Auto Executor, Notification) running on GPT-OSS-120B, with Qwen3 embeddings retrieving one of 86 curated error-to-SOP patterns and MCP servers giving read access to MongoDB history, an Oracle spec database, and the file system. Only low-risk actions with backups are auto-executed; the human still makes the fix decision, and over 2,500 lines of hand-written domain prompts carry the verification know-how.
ResultOn two case studies from a 30,132-test flagship SoC project, per-error information gathering fell from 47 min to 2.65 min (94.4%), with 83.3% of the information an engineer would have collected present in the report.
The design choice worth stealing is the explicit line between gathering context, which agents do, and deciding the fix, which they do not, plus a hard command blacklist on top of the whitelist. The headline 94.4% rests on exactly two hand-picked cases against an interview-estimated baseline, and the 3,668 engineer-hour savings is an extrapolation, not a measurement. The system has not been deployed to production and the authors list these limits themselves.
ProblemSoC simulation logs run to a million lines, and the same test on two design labels prints messages differently and in a different order, so diffing a failing log against a passing one by hand is slow and unreliable.
ApproachLogMiner is a Plotly Dash dashboard that buckets log lines into tabs (UVM, errors, tool, VIP, register writes, boot) and adds a semantic comparator: the all-MiniLM-L6-v2 sentence-transformer is fine-tuned with contrastive loss on Samsung log lines, and cosine similarity against a user-built reference log surfaces matching, missing, and out-of-order lines. The user picks a similarity threshold from a precision/accuracy sweep.
ResultAcross a 5000-test regression the paper reports debug turnaround dropping from 5 min to 1 min on a 10K-line log and from 3 hrs to 12 min on a 1M-line multi-boot log, with the fine-tuned model catching 98% of similar line pairs at a 0.846 threshold.
The useful part is fine-tuning a tiny embedding model so that engineer-authored messages with different wording still line up, which beats fuzzy string matching for cross-label comparison. It is a modest, well-scoped tool rather than an AI breakthrough, and the authors are candid that it finds the first divergence point, not the root cause. The baseline times are averaged self-reports from a 20-person Samsung team, and the tool is proprietary, so treat the numbers as directional.
ProblemSoC testbench bring-up and post-simulation debug lean on manual log reading, waveform staring, and rerunning simulations, and ignore the reusable data piled up from earlier projects.
ApproachA hybrid pipeline: before simulation, register init sequences are checked against a statistical baseline from past projects using rule checks, RapidFuzz and BERT-embedding name matching, and an Isolation Forest anomaly detector; after simulation, Python scripts use UVM checker messages to pull AHB/APB/AXI signals from the wave dump and feed them to a trained classifier (six architectures compared, Transformer encoder wins) that flags protocol violations, which rules then map to a testbench line or design update. A FAISS-indexed history of past errors plus a GPT-OSS-120B chat interface let engineers query the accumulated debug log.
ResultSamsung reports an average 56% cut in overall verification effort across deployed projects, one feature going from 15 weeks to 5-6 weeks, and up to 99.5% accuracy for the Transformer encoder on AXI write-channel violation classification.
This is a pragmatic kitchen-sink assembly of familiar ML pieces rather than one new technique, but the pre-simulation register-baseline check is a genuinely useful and cheap idea most teams could copy. The protocol classifier is trained on synthetically injected violations, so the near-99% numbers say more about the generator than about real bugs. The 56% effort figure comes from a single engineer's timeline estimate on Samsung projects, with a stated 12-week build cost and 2 weeks per new project to port.
Regression and coverage closure: agents as plumbing
The regression papers are less about clever models and more about wiring: which tests to run after a change, when a block is stable enough to promote to chip level, and how to stop reruns from burning the farm. Read the numbers with the vendor dependency in mind; most of these flows sit on top of Cadence Verisium or SimAI.
ProblemAfter each RTL drop, sanity regression still depends on engineers hand-picking tests, reading hundreds of failure logs and hunting through waveforms, costing 4 to 8 engineer-hours per iteration and giving inconsistent results.
ApproachSmart Sanity Regression (SSR) is a one-command orchestration layer over Cadence Verisium apps: CodeMiner plus AutoFocus pick tests correlated with the RTL diff against a golden baseline session, Manager plus AutoTriage cluster failures with unsupervised-then-supervised ML and rerun one representative per cluster with waveforms, and WaveMiner diffs those against golden waveforms to rank suspect signals. The contribution is the staged data handoff and rerun policy, not new algorithms.
ResultAcross three production IPs, SSR ran 7 to 10% of the full suite, cut runtime by up to 89% (18 h to 2 h on IP1), compute by over 90% (5,500 to 450 core-hours on IP3), and manual-flow turnaround by about 55%, while keeping 100% functional coverage on modified blocks.
The most transferable finding is that predefined sanity lists only touched 5 to 20% of the modules that actually changed, so change-aware selection sometimes runs more tests, not fewer, and that is the right outcome. Clustering to one waveform rerun per failure group is a simple policy anyone can copy regardless of tooling. The flow is entirely Cadence-dependent, the paper's own headline numbers drift between abstract and conclusion (92% vs 91% compute, 56% vs 54% TAT), and the waveform signal ranking only lands the true root signal in the top three 50 to 87% of the time.
ProblemFlat, monolithic regression pipelines rerun huge test sets with no awareness of design hierarchy or which block a change touched, so chip-level runs start on unstable blocks, engineer sanity runs go untracked, and tests silently never get executed.
ApproachThe authors split regression into three scopes (an engineer's own sanity runs, change-triggered block runs, and gated chip-level runs) and connect them through RabbitMQ publish-subscribe bridges; a gate agent only promotes a block to chip regression once its pass rate clears a threshold. Agents are typed as regression (decide what to run), bridge (route results between tiers) or operation (stateless workers for dispatch, failure classification and owner routing via filesystem, REST and JIRA MCP servers); no specific LLM is named and much of the logic is policy-driven.
ResultOn a production SoC, 2,892 of 20,766 block tests (13.9%) had never run before the first chip regression under the old flow; with tier gating, chip regression started at 91.2% and 83.1% block pass rates instead of roughly 23.6%, and an ablation without the block agent delayed chip regression by about 36%.
The useful idea here is organizational rather than algorithmic: treat engineer sanity runs and block-level change regressions as first-class tiers with explicit promotion criteria, so the chip-level farm stops burning cycles on blocks that are obviously broken. The message-broker decoupling and the ablation showing that direct agent-to-agent polling scales badly are practical lessons for anyone wiring up regression automation. This is the architecture half of a Samsung pair; its companion paper on multi-agent triage benchmarks the LLM debugging agents, while this one contains no LLM evaluation, reports only two representative blocks, and admits full quantitative evaluation is still underway.
ProblemStatic ranking of regression tests by hand-tuned weights (failure recency, coverage gain, runtime) goes stale as RTL and coverage goals change, wasting simulation cycles and delaying coverage closure.
ApproachA supervised classifier (Random Forest chosen over logistic regression and gradient boosting, trained with scikit-learn) scores each test and seed on five features such as coverage novelty, failure likelihood, coverage-per-second and seed-outcome entropy, then feeds a prioritized list to the unchanged UVM regression scheduler. Retraining happens automatically every 2 to 3 regressions, low-utility tests are kept for occasional exploration, and Cadence SimAI is used for log extraction and generating the optimized test-set files.
ResultOn two multimedia IPs (814 and 24,000 tests) the flow cut test count about 65%, regression time roughly 66 to 71% versus random execution and about 31% versus ranking, while IP1 regained 286,354 of 308,999 coverage bins (92.7%).
The concrete details are the value here: a small feature set, a model family comparison, a cold-start recipe that falls back to heuristic ranking until about 1,000 samples exist, and the decision to demote rather than delete low-value tests so coverage stagnation can still be probed. The work is incremental relative to prior ML test-prioritization papers, and its claim of vendor independence sits awkwardly with results generated through Cadence SimAI. Absolute closure numbers, a 25% faster sign-off, and the subsystem-level 2 to 3x claim are given without methodology, and there is no held-out bug-finding evidence.
- US 2026Multi-Agent Orchestration for Autonomous Regression Management (Samsung) — Regression automation can launch and watch jobs, but a human manager still has to read failures, decide who owns them, spot duplicates and replan, which makes triage the throughput bottleneck.
- US 2026Etabot: Multi-Agent Verification Management with Chat-Accessible Midpoint Metrics and Finish-Date Forecasts (Silicon Labs) — Answering 'where are we and when will we finish' means hand-collecting logs, merging coverage, separating infrastructure noise from real design failures and writing up status, which eats engineering time every week.
- Europe 2025Accelerating Coverage Closure with Reinforcement Learning: A Case Study on FSM Verification (Verification Consulting doo) — Most seeds in a constrained-random regression add nothing to coverage yet still burn simulator licences and wall-clock time, and the sanity regressions gating every commit pay that cost repeatedly.
AI meets formal: ground truth for free
Formal tools are a natural partner for LLMs because the tool checks the answer. A generated assertion either proves or it does not, and a counterexample is a precise, machine-readable explanation of what went wrong. NVIDIA and Cadence both leaned on that property this year.
ProblemWorking out why a formal property failed means hand-tracing a multi-cycle counterexample against the RTL and the spec, which can eat hours or days per bug.
ApproachFVDebug turns a Jasper counterexample into a causal DAG by recursively calling the tool's visualize -why command, then runs an o3-mini pipeline over it: a Graph Scanner that scores every node with a forced pro-and-con argument prompt, an Insight Rover that agentically walks the graph to build and rank competing failure hypotheses, and a Fix Generator that produces RTL patches via five prompting strategies with consensus scoring. Output is a report with ranked hypotheses, a cycle timeline, and diff-ready fixes.
ResultOn the 38-case SVA-Eval-Human benchmark it reached 0.956 Quality@Best for root-cause hypotheses, 71.1% Pass@1 and 86.8% Pass@5 for fixes validated by re-running Jasper, versus 60.5% Pass@1 for a direct LLM baseline.
The interesting idea is not the LLM but the data structure: building an explicit causal graph from the model checker's own dependency query, so the model reasons over signal-at-cycle nodes instead of a flat trace dump. The ablations back this up, since dropping the causal narrative stage collapses hypothesis quality from 0.956 to 0.795. Caveats: the benchmark is small and mostly simple designs, quality on the two CVA6 processor failures drops to 0.713 with no fixes attempted, the two proprietary cases are masked so nobody can reproduce them, and the whole thing is wired to Cadence Jasper TCL commands.
ProblemThree front-end formal tasks, pulling a verification plan out of the spec, standing up the formal environment, and writing routine SVAs, are slow, expert-dependent, and where checks get missed.
ApproachSIGMA chains an in-house GenAI platform that reads architecture and micro-architecture specs and emits a classified verification plan (Gemini, GPT-OSS-120B and a Llama Nemotron variant were compared), a Python script that parses the DUT ports and generates the top, checker, file list and Makefile, and a Copilot-based assistant that drafts SVAs for basic checks with RAG over previously corrected assertions for harder ones. Every stage keeps an engineer review step before sign-off.
ResultOn a PCIe sequence-number FSM verified with both flows, plan extraction went from about 2 weeks to 3 days (75%), environment setup from a week to 2 days, SVA drafting saved roughly 1.5 weeks, and total effort fell from 4 to 3 months; four further PCIe blocks show 1 to 2 month savings against extrapolated baselines.
This is a workflow paper: three modest automations stitched together with human review, and the RAG trick of storing engineer-corrected SVAs so the assistant stops repeating the overlapping-implication mistake is the most transferable detail. Nothing here is technically novel and the environment generator is plain scripting. Only one block got a true side-by-side comparison; the other four baselines were estimated from gate and I/O counts, and the LLM comparison is a single-design ranking the authors themselves say may not generalize.
ProblemFormal teams own libraries of reusable assertion VIPs for common structures like FIFOs and arbiters, but hooking them up to every instance in a large RTL codebase is slow, needs VIP expertise, and gets skipped under schedule pressure.
ApproachA four-stage pipeline strips comments and preprocessor noise from the RTL, splits it into syntactically complete chunks under the model's token limit, filters chunks by FIFO and arbiter naming conventions, and asks an LLM to emit the VIP binding for each. The prompt is augmented either with a one-shot example (in-context learning on an internally fine-tuned Mixtral 8x7B) or with retrieved snippets from a vector store of VIP docs and prior instantiations (RAG on stock Llama-3-70B-instruct); a post-pass discards outputs with two or more unresolved signals as hallucinations and back-fills FIFO depth and width from source.
ResultRAG with Llama-3-70B produced 7 of 7 correct FIFO VIP instantiations and 11 of 12 correct arbiter ones, versus 4 of 7 and 1 of 12 for the one-shot fine-tuned model and zero for the un-augmented baseline.
Wiring existing checkers to existing modules is a far better-scoped LLM job than writing assertions from scratch, because the output is fully checkable and the model only has to map signal names. The strongest practical message is that retrieval over your own VIP examples beat an in-house fine-tuned model, so you can ride newer general models without retraining. Caveat: the comparison confounds model and augmentation method (Mixtral for ICL, Llama-3 for RAG), the sample is 19 instances of two VIP types, and the chunk filter relies on naming conventions holding across the codebase.
Spec grounding and design understanding
A model that only reads RTL misses everything that happens over time. Two directions showed up in 2026: let the agent run experiments (simulate, probe, replay a counterexample) to learn a block the way an engineer does, and give it retrieval over the project's own spec, tickets, and history so its explanations are anchored in something real.
ProblemLLM agents that only read SystemVerilog miss the time-dependent behavior hidden in RTL, so they produce shallow design descriptions and then fail at downstream jobs such as writing formal properties.
ApproachDUET wraps an experimentation loop around the agent: the LLM proposes a hypothesis about the design, checks it by invoking EDA tools (Verilator simulation, Jasper formal runs, waveform dumps, Yosys analysis, and a sub-agent that turns a Jasper counterexample into a simulation testbench), then folds the observed behavior back into its understanding before retrying. The evaluated flow ran GPT-5.0 inside an agentic formal-verification pipeline and told the agent to experiment whenever a formal testbench failed.
ResultOn a round-robin arbiter with ten planned properties, the experimentation-enabled flow proved 6 properties against 3 for the no-experimentation baseline, and every improved property used the counterexample-replication sub-agent.
The useful idea is procedural rather than architectural: let the agent run cheap simulations to falsify its own guesses instead of trusting a one-shot RTL readthrough, which is how human DV engineers actually learn a block. The result that counterexample replication drives most of the gains is a practical hint for anyone wiring an LLM to Jasper. The caveat is scale: one small arbiter, one attempt per property, a single model, and the authors admit the agent still tried to cheat by forcing signals and mostly ignored the formal and analysis tools it was offered.
ProblemOn a large SoC the spec, RTL, test plans, regression logs, and Jira tickets live in different systems and change at different rates, so tracing a failure back to its requirement or to a prior fix depends on tribal knowledge and slow manual digging.
ApproachThe team built a debug assistant with two retrieval memories: a short-term store over MongoDB regression logs and recent diffs, and a long-term store over Oracle tables plus a HippoRAG/Neo4j knowledge graph linking spec sections, block versions, test plans, results, and issues. A small decision model (MiniMax-M2) classifies which maturity stage (ML1 to ML4) a query belongs to and sets the STM/LTM retrieval mix, then an action model (GLM-4.6) reasons over the gathered evidence to write a root-cause explanation.
ResultReplaying 34 weeks of history covering 398 issues from a real SoC program, the full system cut estimated debug time by up to 27 percent, versus 11 percent for an equal-weight dual memory and 0 percent for keyword search.
The interesting engineering choice is admitting that early-project debugging needs fresh logs while late-project debugging needs relational history, and letting a cheap model pick the blend per query rather than tuning one RAG for everything. Compared with its companion paper on RL-weighted knowledge graphs, this one is about retrieval and explanation for debug, while the other is about predicting which tests to rerun after a design change. Treat the 27 percent as an offline estimate derived from hand-labeled Jira data that the authors themselves call noisy, not as a measured wall-clock saving on live projects.
- US 2026Towards Self-Adaptive SoC Design Verification: KG-Enhanced Generative AI, RL and Backpropagation Debugging (Samsung) — When an IP changes, a static block-IP-test hierarchy is a poor guide to which tests will actually flip, because in practice many result changes show up in IPs that were never edited, so impact-based regression selection wastes runs and misses real effects.
Honest case studies, benchmarks, and what it costs
The healthiest sign in this batch is that people are now measuring. Verilab counted fix iterations and dollars; Minnesota and Synopsys released a benchmark; a startup wrote a whole paper about token accounting. None of these are glamorous, and all of them will save you a bad quarter.
ProblemNobody had measured, side by side, how well a terminal coding assistant can build a real verification IP in SystemVerilog UVM versus Python cocotb plus PyUVM.
ApproachThe authors scripted Aider with three frontier models (Claude Opus 4, Gemini 2.5 Pro, OpenAI o3) through an identical prompt sequence to generate an APB3 VIP and self-checking testbench in both ecosystems, with and without a coding-conventions file, then counted fix iterations, inspected waveforms, and logged API cost.
ResultNo model produced compile-clean code on the first try in either language; UVM-SV testbenches ran after 3 to 6 fix iterations, while PyUVM needed 19 to 33 iterations or was abandoned, at roughly 1 to 30 USD per full run.
This is the most honest datapoint in the batch: the assumption that Python-based testbenches would be easier for LLMs turned out to be wrong, most likely because UVM-SV has far more public example code. Two practical lessons transfer directly to any team: detailed prompts naming agent roles and coverage expectations matter more than the model choice, and human-oriented coding guidelines can make the model drop real protocol logic to satisfy style rules. It is a single APB3 case study, so treat the iteration counts as indicative rather than a benchmark.
ProblemThere are public benchmarks for LLM-written RTL but none for LLM-written UVM environments, so there is no repeatable way to compare how good a model's testbench actually is.
ApproachThe authors take five already-verified DUTs from the RTLLM suite, hand the model a fixed interface, top module and a structured prompt listing every UVM class it must produce, then compile in VCS with up to four fix-the-syntax retries, simulate for coverage, and lint the generated classes with Euclide. They ran the loop five times each for ChatGPT-4o, Gemini 1.5 Pro and Llama 3.2, releasing the harness under an MIT licence.
ResultAcross five DUTs, Gemini 1.5 Pro built 88% of the time with 79.3% average coverage, ChatGPT-4o 84% and 70.6%, and Llama 3.2 64% and 46.8%; FSM and covergroup coverage were poor for every model.
The scoring design is the contribution worth stealing: fixing the harness and interface up front so only the class-based code varies, then judging on build rate, per-metric coverage and lint counts rather than on whether the output looks plausible. The numbers confirm what most of us suspect, namely that models reach high line and toggle coverage with naive random sequences and then stall on branch, FSM and hand-written covergroups because they never write directed or constrained stimulus. Caveat: the DUTs are toy-sized, the coverage figure is a VCS average that hides weak metrics, the human-driven prompt refinement loop is not fully automated, and generated scoreboards often flagged false failures on known-good designs.
ProblemOnce LLM triage and debug agents run inside nightly regressions, nobody in the EDA stack can say what a given test, agent, or heuristic change cost in tokens, so spend can balloon unnoticed or compete for on-prem GPU time.
ApproachPassive Token Accounting reads the usage fields already present in provider responses through the open-source dhenara-ai client, converts them to USD with a per-model rate table, rolls them up per node and per agent inside the DAG-based agent runtime, and appends everything to a per-regression costs.json that a stateless gateway serves to a UI. Budget knobs let a deep-debug agent stop sub-loops at a cost or token ceiling and swap to a cheaper model when a soft cap is reached.
This is the boring infrastructure that every team adopting LLM debug agents will need within a quarter, and the paper's argument that accounting belongs in the client layer rather than an HTTP proxy is sensible and portable across providers. It is a vendor product description with an open-source core library, so the novelty is modest and the evaluation is anecdotal. The honest gap is that the per-agent stopping rules exist but cross-regression budgets are still enforced by a human watching a dashboard.
- US 2026ChipAgents in Practice: Lessons from One Year of Agentic AI EDA Deployment (ChipAgents) — Design teams face growing complexity and thick layers of legacy IP, and having engineers hand-craft prompts for each agent task does not scale.
- Europe 2025GAIL-V: Generative AI Leveraged Verification (Arm) — Teams are adopting LLMs for verification one engineer and one script at a time, with no shared way to decide which parts of the flow actually suit a model or to measure how well it does there.
- Europe 2025LLM-based Functional Coverage Generation and Auto-Evaluation Framework (Masaryk University) — Functional coverage is a low-risk place to try LLM code generation, but there was no reproducible way to score what small, locally run models actually produce.
Coming up: DVCon India 2026
The selected-paper list for DVCon India 2026 was published this month and is the most AI-dense program of the three events. Papers are not on the archive yet, so titles only. The ones I have flagged to read when they land:
- Spec to Bug Evidence: An Agentic AI Framework Accelerating Formal Verification Bug Discovery (Devansh Shah, Neha Joshi, Anshul Jain)
- AI Agents for Data-Driven Reset Abstraction Decisions to Accelerate Formal Proof Convergence (Anshul Jain, S R Pavitra, Sharika Shaju, Neha Joshi)
- FloatFix: An Agentic AI Debugger for Floating-Point Arithmetic in Formal Equivalence Verification (Suraj Kamble, Mohit Choradia, Vichal Verma)
- Debug Assist: An LLM-Guided Framework for Debugging FPV Failures (Kevin Bhensdadiya, Vichal Verma, Ajay Kumar Kolluri)
- Beyond Syntax: Ensuring the Safety and Style of AI-Generated Hardware (Amarnath D)
- PPA_CoPilot: An Agentic Framework for RTL Quality Analysis and PPA Optimization (Srinivasa Sudhakar Tipparaju et al.)
- LLM-VPBench: An Open Benchmark Suite for Evaluating LLM-Aided SystemC TLM-2.0 Virtual Platform Generation (Subrat Katiyar, Mahantesh Danagouda)
- AI Driven Regression Optimization with Cadence Verisium SimAI and AI-Assisted Regression Optimization Using Synopsys VSO.AI, two papers from the same team (Vishnu G, Aravind R K et al.), which should make for a rare like-for-like vendor comparison
- AI-Driven RTL Change-Aware Testlist Generation for RISC-V Core Verification and AI-Driven Coverage-Directed Smoke Regression Optimization via Greedy Set Cover (Abhishek Rajgadia, Shubham Singla, Radha Govindaradjou et al.)
- FunCovr.ai: AI that Generates Sharper Coverage and Smarter Closure (Mahesh Shinde et al.)
What this means for your team
Reading twenty-one papers back to back makes the pattern hard to miss. The wins that survive their own caveats share three properties: the model works on data your team already produces, a tool or a human checks the answer before anything changes, and the baseline was measured rather than remembered. Here is how I would act on that.
If you read only one paper from this list, make it FVDebug. If you read only one section, make it the case studies in theme five, because the failures reported there will save you more time than the successes.
Sources
- DVCon Proceedings Archive, 2026
- DVCon Proceedings Archive, 2025
- DVCon U.S. 2026 best paper winners, attendance, and highlights (Accellera press release)
- DVCon U.S. 2026 program announcement and AI panel
- DVCon U.S. 2026 tutorials and workshops
- DVCon India 2026 selected paper list (PDF)
- DVCon Europe 2025 conference program (PDF)
- Individual paper PDFs are linked from each card above.
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